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The OMAP1612 processor is a single-chip application processor that supports all cellular standards, and complements any modem or chipset and any air interface. It is intended for high-volume wireless OEMs and ODMs and is not available through distributors. The OMAP161x devices offer application performance 1.5x greater than the previous generation. The ARM and DSP cores have multiple hardware-based application accelerators, including a dedicated on-chip 2D graphics acceleration engine, eliminating the need for discrete graphics chips. Multimedia acceleration also provides a 70 percent performance increase for audio applications, while Java™ acceleration provides an 8x performance improvement. Along with the increased performance, OMAP161x processors have standby power consumption levels among the lowest in the industry, dropping to less than 10 micro-Amperes (µA) of battery power. The OMAP161x processors also feature a dedicated sub-system which includes a secure bootloader, secure mode of operation, secure RAM and ROM, and hardware accelerators for several security standards. The OMAP1612 processor includes all of the capabilities on the OMAP1610 and OMAP1611 devices with the added benefit of 128 megabits (Mb) or 256 Mb of stacked mobile double data rate (DDR) synchronous dynamic memory (SDRAM). This DDR memory allows for a 100 MHz interface clock to memory while providing memory access speeds up to 200 MHz. With stacked memory, mobile device manufacturers can design a system that benefits from expanded memory storage and still occupy a very small footprint. OMAP1612 Features: Low-Power, High-Performance CMOS Technology - Low-voltage 130 nm technology
- 1.1 - 1.5V cores; 1.8 - 3.0V IO
- Consumes less than 10 µA in standby mode
- Split power supplies for application processing, digital baseband and real-time clock enable precise control over power consumption
- Optimized clocking and power management: only two clocks required at 13 MHz and 32 kHz
TMS320C55x DSP core subsystem - Up to 204 MHz (maximum frequency)
- 32K x 16-bit on-chip dual-access RAM (DARAM) (64 KB)
- 48K x 16-bit on-chip single-access RAM (SARAM) (96 KB)
- 24 KB I-cache
- One/two instructions executed per cycle
- Video hardware accelerators for DCT, iDCT, pixel interpolation, and motion estimation for video compression
ARM926TEJ core subsystem - Up to 204 MHz ARM926TEJ V5 architecture (maximum frequency)
- 16KB I-cache; 8KB D-cache
- Java acceleration
- Support for 32-bit and 16-bit (thumb mode) instruction sets
- Data and program MMUs
- Two 64-entry translation look-aside buffers (TLBs) for MMUs
- 17-word write buffer
Security Acceleration in Hardware - Secure bootloader
- 48 kB of secure ROM
- 16 kB of secure RAM
- Hardware acceleration for security standards and random number generator
- Unique die ID cell
- Third-party Security software library
Memory Traffic Controller (TC) - 16-bit EMIFS external memory interface
- 16-bit EMIFF external memory interface
Mobile DDR and 128 Mb/256 Mb stacking memory options 2-Mb ISRAM Application Subsystem - Supports leading operating systems
- DMA with 4 physical and 17 logical channels and a dedicated 2D graphics engine
- USB On-the-Go (OTG)
- Two SD/MMC/SDIO ports
- Two high-speed 3.68 MHz UARTs
- I2C controller
- Two high-speed 3.68 MHz UARTs
- uWire
- CompactFlash
- Parallel and compact camera ports
- Enhanced Debug Trace (ETM) for debug
- Fast IrDA (FIR)
- SPI
- LCD controller
- 54-Mbps interface to WLAN 802.11a/b/g
- Comprehensive memory controller for interfaces to:
- 128 MB of mobile SDRAM and mobile DDR
- 256 MB Flash (for burst, programmable NOR flash)
289-ball, 12 mm x 12 mm MicroStar BGA™ Package
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